Taimur Rabuske
Analog and mixed-signal IC designer with a PhD in microelectronics and more than fifteen years in CMOS silicon, currently at Analog Devices. I own subsystems end to end — feasibility study and architecture exploration, specification derivation, transistor-level design, verification, layout sign-off, tape-out and bench validation — across data converters, clocking, power management and high-speed links.
LOCATION: Wilmington, Massachusetts, USA
PROCESSES TAPED OUT: 500 nm to 5 nm
SCOPE: ARCHITECTURE → DESIGN → SILICON
RECORD: 48 PAPERS / 1 PATENT GRANTED, 6 PENDING
What I bring
Subsystems, not just blocks
At Analog Devices I take subsystems from feasibility study and architecture exploration through implementation, verification and validation, and on into the lab with the silicon measurement team. Every one has been a new architecture rather than a port of existing IP; six patent applications are under examination on the results.
Converters, clocks, power and links
SAR, charge-sharing, ΣΔ and high-speed flash ADCs; clock synthesis and LC, ring, relaxation and injection-locked oscillators; LDOs with wideband PSR, references and biasing; a die-to-die SerDes link; and sensor and biomedical front-ends.
Eight process generations
Prototypes and products taped out from 0.5 µm to 5 nm, in bulk CMOS, SOI and FinFET. On the research prototypes I ran the whole path myself — specification, architecture, schematic, custom layout, DRC/LVS sign-off, tape-out, PCB, firmware and bench characterisation.
Specs that reach past the die
Derived the specifications for complete instruments, not only the chip: partitioning between silicon, board and software, then the boards, drivers and measurement software that had to exist around it for the prototype to prove anything.
An MSc in computer science, and Python everywhere
Behavioural modelling, gm/ID sizing, simulation-driven optimisation, test automation and bench data analysis. Published in-house EDA tooling: PyCO, a parallel genetic-algorithm optimiser for analog circuits, and Polymath, a platform for rapid development of modular EDA tools.
Research led, researchers grown
Led analog and mixed-signal circuit research at INESC-ID: supervised six doctoral and six MSc researchers, wrote the proposals that funded the work, sat on the Scientific Council, and designed circuits for industry partners' commercial products under collaboration agreements.
Silicon record
Chips taped out across eight process generations, in bulk CMOS, SOI and FinFET — research prototypes I designed and characterised end to end, and production subsystems at Analog Devices.
Index
Expertise
- SAR, charge-sharing, charge-redistribution, ΣΔ and high-speed flash data converters
- Clock synthesis, and LC, ring, relaxation and injection-locked oscillators
- LDOs with wideband PSR, references, biasing and reference buffers
- Die-to-die SerDes serialisers and deserialisers, and high-speed links
- Dynamic comparators and latches, with background offset and noise calibration
- Feasibility study, architecture exploration and specification derivation
- Behavioural modelling; noise, offset, matching, settling and jitter analysis
- PVT, corner and Monte Carlo verification; PSS, PXF and PNOISE for comparators
- Custom layout, DRC/LVS/PEX sign-off, tape-out, bring-up and bench characterisation
- Low-voltage, low-power CMOS, down to 0.35 V supplies
- Cadence Virtuoso, Spectre and the analog verification flow; HSPICE
- Python for modelling, sizing, optimisation, test automation and data analysis
- In-house EDA tooling: gm/ID sizing, genetic-algorithm optimisation, modular EDA platforms
- Static and dynamic converter characterisation on the bench
- PCB design, instrument control and firmware for prototype test benches